Total number of timesteps to generate. Each scenario gets an equal share.
Generate Clock...
Generate Reset...
Generate FSM...
Duplicate Signal(s)
Delete Signal(s)
Generate Signal
Verilog RTL Generator
Configuration
Module
Testbench
Generate RTL via AI (Recommended)
AI will generate synthesizable RTL module and testbench based on your signal list, scenarios, and waveform data. Uses waveform timing to create accurate stimulus in the testbench.
Manual Template Generation
Sequential always block
Generate clocked always @(posedge clk)
Asynchronous reset
Use always @(posedge clk or negedge rst_n)
Generate testbench
Create tb_module.v with waveform stimulus
MODULE RTL
AI GENERATED
// Click "Generate RTL with AI" or "Generate Template" on the Configuration tab
TESTBENCH
AI GENERATED
// Click "Generate RTL with AI" or "Generate Template" on the Configuration tab